STRATIX 10 FPGA AND SOC
Stratix® 10 FPGAs and SoCs deliver breakthrough advantages in performance, power efficiency, density, and system integration: advantages that are unmatched in the industry. Featuring the revolutionaryHyperFlex™ core fabric architecture and built on the Intel 14 nm Tri-Gate process, Stratix 10 devices deliver 2X core performance gains over previous-generation, high-performance FPGAs with up to 70% lower power.
Stratix 10 FPGA and SoC system integration breakthroughs include:
- Heterogeneous 3D System-in-Package (SiP) integration
- The highest density FPGA fabric with up to 5.5 million logic elements (LE)
- Up to 10 TFLOPS of IEEE 754 compliant single precision floating point DSP throughput
- Secure Device Manager (SDM) with the most comprehensive security capabilities
- Integrated quad-core 64 bit ARM® Cortex®-A53 hard processor system up to 1.5 GHz
- Complementary optimized and validated Enpirion® power solutions
These unprecendented capabilities make Stratix 10 devices uniquely positioned to address the design challenges in next generation, high performance systems in virtually all end markets including wireline and wireless communications, computing, storage, military, broadcast, medical, and test and measurement.
Stratix 10 Family Variants
| Variant | Description |
|---|---|
| Stratix 10 GX FPGAs |
Stratix 10 GX FPGAs are designed to meet the high-performance demands of high-throughput systems with up to 10 TFLOPS of floating point performance and transceiver support up to 30 Gbps for chip-module, chip-to-chip, and backplane applications. |
| Stratix 10 SX SoCs |
Stratix 10 SX SoCs feature hard processor system with 64 bit quad-core ARM Cortex-A53 processor available in all densities in addition to all the features of Stratix 10 GX devices. |
| Stratix 10 GT FPGAs |
For the most demanding applications requiring next generation standards support, Stratix 10 GT FPGAs support transceivers with a path to data rates up to 56 Gbps. |
Stratix 10 GX/SX Device Family Table
| Download PDF Family table |
||||||||||
| Part # Reference |
10SG050 10SX050 |
10SG065 10SX065 |
10SG085 10SX085 |
10SG110 10SX110 |
10SG165 10SX165 |
10SG210 10SX210 |
10SG250 10SX250 |
10SG280 10SX280 |
10SG450 10SX450 |
10SG550 10SX550 |
|---|---|---|---|---|---|---|---|---|---|---|
| Stratix 10 Product Line |
GX 500 SX 500 |
GX 650 SX 650 |
GX 850 SX 850 |
GX 1100 SX 1100 |
GX 1650 SX 1650 |
GX 2100 SX 2100 |
GX 2500 SX 2500 |
GX 2800 SX 2800 |
GX 4500 SX 4500 |
GX 5500 SX 5500 |
| Equivalent LEs1 |
484,000 | 646,000 | 841,000 | 1,092,000 | 1,624,000 | 2,005,000 | 2,422,000 | 2,753,000 | 4,463,000 | 5,510,000 |
|
Adaptive Logic Modules |
164,160 | 218,880 | 284,960 | 370,080 | 550,540 | 679,680 | 821,150 | 933,120 | 1,512,820 | 1,867,680 |
| ALM Registers | 656,640 | 875,520 | 1,139,840 | 1,480,320 | 2,202,160 | 2,718,720 | 3,284,600 | 3,732,480 | 6,051,280 | 7,470,720 |
| Hyper-Registers from HyperFlexTMArchitecture | Millions of Hyper-Registers distributed throughout the monolithic FPGA fabric | |||||||||
| Programmable Clock Trees Synthesizeable | Hundreds of synthesizable clock trees | |||||||||
|
Maximum |
24 | 24 | 48 | 48 | 96 | 96 | 144 | 144 | 72 | 72 |
|
GXT Full Duplex Transceiver Count |
16 | 16 | 32 | 32 | 64 | 64 | 96 | 96 | 48 | 48 |
|
GX Full Duplex Transceiver Count |
8 | 8 | 16 | 16 | 32 | 32 | 48 | 48 | 24 | 24 |
| M20K Memory Blocks |
2,196 | 2,583 | 3,477 | 4,401 | 5,851 | 6,501 | 9,963 | 11,721 | 7,033 | 7,033 |
| M20K Memory (Mb) |
43 | 50 | 68 | 86 | 114 | 127 | 195 | 229 | 137 | 137 |
| MLAB Memory (Mb) |
3 | 3 | 4 | 6 | 8 | 11 | 13 | 15 | 23 | 29 |
|
Variable-Precision Digital Signal Processing (DSP) Blocks |
1,152 | 1,440 | 2,016 | 2,520 | 3,145 | 3,744 | 5,011 | 5,760 | 1,980 | 1,980 |
| 18 x 19 Multipliers |
2,304 | 2,880 | 4,032 | 5,040 | 6290 | 7,488 | 10,022 | 11,520 | 3,960 | 3,960 |
| Fixed Point Performance (TMACS)2 | 4.6 | 5.8 | 8.1 | 10.1 | 12.6 | 15.0 | 20.0 | 23.0 | 7.9 | 7.9 |
| Single Precision Floating Point (TFLOPS)3 | 1.8 | 2.3 | 3.2 | 4.0 | 5.0 | 6.0 | 8.0 | 9.2 | 3.2 | 3.2 |
| Maximum User I/O Pins | 488 | 488 | 736 | 736 | 704 | 704 | 1160 | 1160 | 1640 | 1640 |
| PCI Express® (PCIe®) Hardened Intellectual Property (IP) Block(s) (up to Gen3) |
1 | 1 | 2 | 2 | 4 | 4 | 6 | 6 | 3 | 3 |
| Secure Device Manager |
AES-256/SHA-256 bitsream encryption/authentication, physically unclonable function (PUF), ECDSA 256/384 boot code authentication, side channel attack protection | |||||||||
| Hard Processor System4 | Quad-core 64 bit ARM® Cortex®-A53 up to 1.5 GHz with 32 KB I/D cache, NEONTM coprocessor, 1 MB L2 cache, direct memory access (DMA), system memory management unit, cache coherency unit, hard memory controllers, USB 2.0 x2, 1G EMAC x3, UART x2, SPI x4, I2C x5, general-purpose timers x7, watchdog timer x4 | |||||||||
Notes:
1. LE counts valid in comparing across Altera devices, and are conservative vs. competing FPGAs.
2. Fixed point performance assumes the use of of pre-adder.
3. Floating point performance is IEEE 754 compliant single precision.
4. Quad-core ARM Cortex-A53 hard processor system only available in Stratix 10 SX SoCs.
Stratix 10 GX/SX Package Options & I/O Pins
(General-Purpose I/O Pins, 3V I/O Pins, LVDS Pairs, Transceivers)1,2
| Download PDF Package Table1,2 | ||||||||||
| Part # Reference |
10SG050 10SX050 |
10SG065 10SX065 |
10SG085 10SX085 |
10SG110 10SX110 |
10SG165 10SX165 |
10SG210 10SX210 |
10SG250 10SX250 |
10SG280 10SX280 |
10SG450 10SX450 |
10SG550 10SX550 |
|---|---|---|---|---|---|---|---|---|---|---|
| Stratix 10 Product Line |
GX 500 SX 500 |
GX 650 SX 650 |
GX 850 SX 850 |
GX 1100 SX 1100 |
GX 1650 SX 1650 |
GX 2100 SX 2100 |
GX 2500 SX 2500 |
GX 2800 SX 2800 |
GX 4500 SX 4500 |
GX 5500 SX 5500 |
|
F1152 Pin 35mm x 35mm, 1.0mm pitch |
344, 8, 172, 24 |
344, 8, 172, 24 |
- | - | - | - | - | - | - | - |
|
F1760 Pin 42.5mm x 42.5mm, 1.0mm pitch |
488, 8, 240, 24 |
488, 8, 240, 24 |
688, 16, 336, 48 |
688, 16, 336, 48 |
688, 16, 336, 48 |
688, 16, 336, 48 |
688, 16, 336, 48 |
688, 16, 336, 48 |
- | - |
|
F2112 Pin 47.5mm x 47.5mm, 1.0mm pitch |
- | - |
736, 16, 360, 48 |
736, 16, 360, 48 |
- | - | - | - | - | - |
|
F2112 Pin 47.5mm x 47.5mm, 1.0mm pitch |
- | - | - | - |
648, 24, 312, 72 |
648, 24, 312, 72 |
648, 24, 312, 72 |
648, 24, 312, 72 |
- | - |
|
F2112 Pin 47.5mm x 47.5mm, 1.0mm pitch |
- | - | - | - |
464, 32, 216, 96 |
464, 32, 216, 96 |
- | - | - | - |
|
F2112 Pin 47.5mm x 47.5mm, 1.0mm pitch |
- | - | - | - | - |
- |
- | - |
648,24, 312, 72 |
648,24, 312, 72 |
|
F2397 Pin 50mm x 50mm, 1.0mm pitch |
- | - | - | - | - | - |
1160, 8, 576, 16 |
1160, 8, 576, 16 |
1256, 8, 624, 16 |
1256, 8, 624, 16 |
|
F2397 Pin 50mm x 50mm, 1.0mm pitch |
- | - | - | - |
704, 32, 336, 96 |
704, 32, 336, 96 |
704, 32, 336, 96 |
704, 32, 336, 96 |
- | - |
|
F2597 Pin 52.5mm x 52.5mm, 1.0mm pitch |
- | - | - | - | - | - |
432, 48, 216, 144 |
432, 48, 216, 144 |
- | - |
|
F2597 Pin 55mm x 55mm, 1.0mm pitch |
- | - | - | - | - | - | - | - |
1640, 8, 816, 16 |
1640, 8, 816, 16 |
Notes:
- A subset of pins for each package are used for high-voltage, 3.0 V and 2.5 V interfaces.
- Select devices available with pin migration from Arria® 10 device family to Stratix 10 device family. Contact Altera for more information.
- All data is preliminary, and may be subject to change without prior notice.
Dowload the Stratix 10 Device Family Table (PDF) to view the Stratix 10 FPGA and SoC family package plans with vertical migration support.
Stratix 10 FPGA and SoC Benefits
Achieve Performance Breakthroughts with Industry’s Highest Performance FPGAs and SoCs
- Ground breaking HyperFlex architecture delivering 2X the core performance gains
- Up to 10 TFLOPS of single-precision floating-point DSP performance
- Quad-core 64 bit ARM Cortex-A53 hard processor subsystem operating up to 1.5 GHz
Break Through the Bandwidth Barrier
- Up to 144 transceivers with data rates up to 30 Gbps deliver 4X serial transceiver bandwidth from previous generation FPGAs for high port count designs
- 30 Gbps backplane capability for versatile data switching applications
- A path to 56 Gbps chip-to-chip/module capability for leading-edge interface standards
- Over 2.5 Tbps bandwidth for serial memory with support for Hybrid Memory Cube
- Over 2.3 Tbps bandwidth for parallel memory interfaces with support for DDR4 at 2666 Mbps
Lower Operating Expense
- Leveraging Intel's leadership in process technology, Stratix 10 devices offer the most power-efficient technologies
- Up to 70% lower power than prior-generation high-end FPGAs and SoCs
- Up to 80 GFLOPS/Watt of single-precision floating point power efficiency
- Quad-core ARM Cortex-A53 processor optimized for performance per watt
Achieve the Highest Level of System Integration
- Largest monolithic FPGA device with 5.5 million logic elements
- Heterogeneous 3D SiP solutions including transceivers and other advanced components
- 64 bit quad-core ARM Cortex-A53 to enable hardware virtualization, system management and monitoring capabilities, acceleration pre-processing, and more.
Obtain the most comprehensive high-performance FPGA security capabilities
- Integrated Secure Device Manager (SDM) for flexibility to update configuration code
- Multi-factor authentication
- Physically Unclonable Function (PUF)
Get Faster Time-to-Market
- Start developing with Arria 10 devices and then migrate to footprint-compatible Stratix 10 devices
- Complementary Enpirion PowerSoCs offer complete and validated power solution for Stratix 10 FPGAs and SoCs higher performance, lower system power, higher reliability, smaller footprint, and faster time-to-market to power Stratix 10 FPGAs and SoCs
Achieve high designer productivity with optimized FPGA and SoC Design Software
- New Spectra-Q™ engine optimized for mulit-million LE FPGA designs providing
- Up to 8X faster compile times
- Significant reduction in design iterations
- Hyper-Aware design flow to optimize designs for HyperFlex architecture
- C-based design entry using the Altera SDK for OpenCL™, offering a design environment that is easy to implement on FPGAs
- Heterogeneous C-based modeling and hardware design with Altera SDK for OpenCL
- Heterogeneous debug, profiling, and whole chip visualization with Altera SoC EDS featuring ARM Development Suite™ (DS-5™) Altera Edition Toolkit

